![]() ![]() The values of the dynamic characteristics of the ADC (SNDR and SFDR) were obtained before and after calibration, and compared. The DDS generator was implemented inside the FPGA. ![]() Its calibration and LUT-based correction were performed using both MATLAB/Simulink and FPGA. The experimental part consists of the implementation of the FPGA-based parametrized 14-bit model pipelined ADC using MATLAB/Simulink. One of the techniques for implementing that is the LUT-based calibration and correction technique inside the FPGA, which was used for obtaining better characteristics of SNDR, SFDR and INL of the FPGA-based parametrized 14-bit model of pipelined ADC. The goal of this work is to provide linearization of the analog-to-digital converter for an FPGA-based Direct Digital Receiver.
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